A power-on reset circuit, sometimes called a power-up clear circuit, is typically used to establish predetermined initial conditions in an integrated circuit while a power supply voltage provided to the integrated circuit increases to a voltage level necessary for proper operation of the integrated circuit. The power-on reset circuit provides a logic signal upon power-up to cause a circuit to power-up in a known state. When the power supply voltage reaches a predetermined voltage level, the power-on reset logic signal is deasserted, allowing the circuit to operate.
In some known power-on reset circuits, a resistive element and a capacitor are used to provide an RC (resistor-capacitor) time constant which is used to establish a relatively long time delay. The relatively long time delay is needed to allow for variations in power supply rise times, power supply transients, and process and temperature variations. The power-on reset signal is deasserted at the expiration of the time delay. However, in some situations, the power-on reset signal may be deasserted before the power supply voltage reaches the predetermined voltage level. For example, the assertion of the power-on reset signal in power-on reset circuits that use an RC time constant is generally dependent on the rise time of the power supply voltage. If the power supply voltage rise time is greater than the RC time constant, the power-on reset signal may be deasserted before the power supply voltage is at the proper level, and the integrated circuit may fail to operate properly.
In other known power-on reset circuits, the power-on reset signal is deasserted when the power supply voltage reaches a predetermined level, and the switching of the power-on reset signal is independent of the rise time of the power supply voltage. However, due to factors such as process and temperature variations, the power-on reset signal may be deasserted before the power supply voltage is at the predetermined level.
In an integrated circuit memory, if the power-on reset circuit is deasserted before an address buffer circuit is properly initialized, an output signal of the address buffer may be undetermined, making it possible for there to be multiple word line selections, resulting in unacceptably high array current.